ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 1 copyright ? 2007, texas instruments incorporated product prev iew information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without notice. www.ti.com www.ti.com dual channel 14 - b it , 125 /105/80/65 msps ad c with parallel cmos /ddr lvds outputs features maximum sample rate: 125 msps 14 - bit resolution with no missing codes 9 2 db crosstalk at 50mhz parallel cmos and ddr lvds output options 3.5 db coarse gain and p rogrammable fine gain up to 6 db f or snr/sfdr trade - off supports sine, lvpecl, lvds & cmos clock inputs & amplitude down to 400 mv p - p digital processing block with offset correction fine gain correction , ( 0.05 db s tep) decimation by 2/4/8 built - in & custo m programmable 24 - tap low / high / band pass filters clock duty cycle stabilizer internal reference, supports external reference also 64 - qfn package ( 9 mm x 9 mm) pin compatible 12 - bit family (ads62p2x) table 1 ads62pxx dual channe l family 125 msps 105 msps 80 msps 65 msps 14 bit ads62p4 5 ads62p44 ads62p43 ads62p42 12 bit ads62p25 ads62p24 ads62p23 ads62p22 11 bit ads62p15 - - - table 2 performance summary ads62p45 ads62p44 ads62p43 ads62p42 fin = 10 mhz 92 92 94 94 sfdr, d bc fin = 170 mhz, 3.5db gain 81 82 83 84 fin = 10 mhz 73.8 73.8 73.9 74 sinad, dbfs fin = 170 mhz, 3.5db gain 70.3 70.3 70.6 70.6 power, mw per channel 396 350 294 259 description ads62p4x is a family of dual channel 14 - bi t a/d converter s with maximum sample rates up to 125 msps. it combines high performance and low power consumption in a compact 64 qfn package. using an internal sample and hold and low jitter clock buffer, the adc supports high snr and high sfdr at high in put frequencies. it has coarse and fine gain options that can be used to improve sfdr performance at lower full - scale input ranges.
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 2 www.ti.com www.ti.com product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue th ese products without notice. ads62p4x includes a digital processing block that consists of several useful & commonly used digital functions such as a dc offset correction, fine gain correction (in steps of 0.05 db), decimation by 2,4,8 & in - built & custom programmable filters. by default, the digital processing block is bypassed & its functions are disabled. two output interface options exist C paralle l cmos and ddr lvds (double data rate). ads62p4x includes internal references while traditional reference pins and associated decoupling capacitors have been eliminated. t he device also supports an external reference mode . the device is specified over the industrial temperature range ( - 40 c to +85 c). reference control interface ina _ p ina _ m clkp clkm vcm s c l k s e n s d a a t a clockgen a v d d a g n d d r v d d d r g n d sha 14 bit adac sha 14 bit adac inb _ p inb _ m output buffers channel b r e s e t c t r l 1 c t r l 2 c t r l 3 output buffers channel a output clock buffer da 0 da 1 da 2 da 3 da 4 da 5 da 6 da 7 da 8 da 9 da 10 da 11 db 0 db 1 db 2 db 3 db 4 db 5 db 6 db 7 db 8 db 9 db 10 db 11 clkout cmos interface da 12 da 13 db 12 db 13 digital encoder digital encoder 14 bit adc 14 bit adc 14 bit 14 bit 14 bit 14 bit digital processing block channel a digital processing block channel b
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 3 product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without no tice. w ww.ti.com www.ti.com offset estimation block 24 tap filter - low pass - high pass - band pass decimation by 2 / 4 / 8 disable offset correction freeze offset correction 0 fine gain ( 0 to 6 db 0 . 5 db steps ) gain correction ( 0 . 05 db steps ) bypass decimation bypass filter to output buffers lvds or cmos 14 bits 14 bits 14 bits 14 bits filter select clipper digital processing block offset correction fine gain gain correction digital filter & decimation from adc output 14 bits 14 bits figure 1 digital processing block diagram package/ordering information (1) product package - lead package designator specified temperature range eco plan (2) lead/ball finish package marking ordering number transport media, quantity ads62p4 5 qfn - 64 rgc - 40c to +85c az62p45 ads62p45 rgc tube ads62p44 qfn - 64 rgc - 40c to +85c az62p44 ads62p44rgc tube ads62p43 qfn - 64 rgc - 40c to +85c az62p4 3 ads62p43rgc tube ads62p42 qfn - 64 rgc - 40c to +85c green (rohs & no sb/br) cu nipdau az62p42 ads62p42rgc tube (1) ja = t bd, jc = t bd. (2) eco plan - the planned eco - friendly classification: green (rohs & no sb/br) : ti defines "green" to mean pb - free (rohs compatible) and free of bromine (br) and antimony (sb) based flame retardants.
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 4 www.ti.com www.ti.com product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue th ese products without notice. absolute maximum rat ings (1) v alue unit supply voltage range, avdd - 0.3 v to 3.9 v supply voltage range, drvdd - 0.3 v to 3.9 v voltage between agnd and drgnd - 0.3 to 0.3 v voltage between avdd to drvdd - 0.3 to 3.3 v voltage applied to external pin, cm (in external reference mode) - 0.3 to 2.0 v voltage applied to analog input pins, ina_p, ina_m, inb_p, inb_m - 0.3v to minimum( 3.6, avdd + 0.3v ) v voltage applied to clock input pins, clkp, clkm - 0.3v to avdd + 0.3v v operating free - air temperature range, t a - 40 to 85 c operat ing junction temperature range, t j 125 c storage temperature range, t stg - 65 to 150 c lead temperature 1.6 mm (1/16 ) from the case for 10 seconds 220 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device . these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute maximum rated conditions for extended periods may affect device reliability .
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 5 product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without no tice. w ww.ti.com www.ti.com recommended operating conditions parameter min typ max unit supplies avdd analog supply voltage 3.0 3.3 3.6 v cmos interface 1.65 1.8 to 3.3 3.6 v drvdd digital supply voltage lvds interface 3.0 3.3 3.6 v anal og inputs differential input voltage range 2 v pp input common - mode voltage 1.5 +/ - 0.1 v voltage applied on cm in external reference mode 1.5 0.05 v clock input ads62p45 1 125 msps ads62p44 1 105 msps ads62p43 1 80 msps input clock sample rate, fs ads62p42 1 65 msps sine wave, ac - coupled 0.3 3.0 v pp lvpecl, ac - coupled 1.6 v pp lvds, ac - coupled 0.7 v pp input clock amplitude differential (v clkp - v clkm ) lvcmos, single - ended, ac - coupled 3.3 v input clock duty cycle 35 % 5 0 % 65 % digital outputs for c load <= 5 pf and drvdd > = 2.2v default strength for c load > 5 pf and drvdd > 2.2v maximum strength output buffer drive strength for drvdd < 2.2v maximum strength cmos interface 5 pf lvds interface , without internal termination 5 pf c load , maximum external load capacitance from each output pin to drgnd lvds interface , with 100 internal termination 10 pf r load , d ifferential load resistance between the lvds output pairs (lvds mode) 100 operatin g free - air temperature, t a - 40 85 c
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 6 www.ti.com www.ti.com product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue th ese products without notice. electrical character istics typical values at 25c, min & max values are across the full temperature range t min = - 40c to t max = 85c, avdd = 3.3v, drvdd = 1.8 v to 3.3v , 50% clock duty cycle, - 1dbfs differential analo g input, internal reference, applies to cmos & lvds interfaces unless otherwise noted. ads62p45 125 msps ads62p44 105 msps ads62p43 80 msps ads62p42 65 msps parameter min typ max min typ max min typ max min typ max unit resolution 14 14 14 14 b its analog input differential input voltage range 2.0 2.0 2.0 2.0 v pp differential input resistance (at dc) , see figure 10 1 1 1 1 m differential i nput c apacitance , see figure 11 7 7 7 7 pf analog i nput b andwidth 450 450 450 450 mhz analog i nput common mode current (per input pin of each channel ) 165 140 110 91 a vcm c ommon m ode v oltage output 1.5 1.5 1.5 1.5 v vcm output current capability 4 4 4 4 ma power supply iavdd analog supply current 232 205 172 152 ma i drv dd output buffer supply current , cmos interface 2.5mhz input signal, no load capacitance (1) 15 13 10.5 9 ma total p ower C cm os interface, drvdd = 1 .8v 792 tbd 700 tbd 587 tbd 518 tbd mw total p ower C lvds interface , drvdd = 3.3v tbd tbd tbd tbd mw global power down 50 tbd 50 tbd 50 tbd 50 tbd mw (1) in cmos mode, the drvdd current scales with the sampling f requency and the load capacitance on output pins .
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 7 product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without no tice. w ww.ti.com www.ti.com electrical character istics typical values at 25c, min & max values are across the full temperature range t min = - 40c to t max = 85c, avdd = 3.3v, drvdd = 3.3 v, 50% clock duty cycle, - 1dbfs differential anal og input, intern al reference, applies to cmos & lvds interfaces, unless otherwise noted. ads62p45 125 msps ads62p44 105 msps ads62p43 80 msps ads62p42 65 msps parameters min typ max min typ max min typ max min typ max unit dc accuracy no missing code s assured assured assured assured dnl differential non - linearity tbd +/ - 0.8 tbd tbd +/ - 0.7 tbd tbd +/ - 0.5 tbd tbd +/ - 0.4 tbd lsb inl integral non - linearity tbd +/ - 3 tbd tbd +/ - 2.5 tbd tbd +/ - 1.5 tbd tbd +/ - 1.5 tbd lsb offset error tbd tbd tbd tb d tbd tbd tbd tbd tbd tbd tbd tbd mv offset error temperature coefficient tbd tbd tbd tbd v/ c offset error variation with supply tbd tbd tbd tbd mv/v there are two sources of gain error C internal reference inaccuracy and channel gain error gain error due to internal reference inaccuracy alone tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd % fs reference gain error temperature coefficient tbd tbd tbd tbd d %/ c gain error of channel alone (1) tbd tbd tbd tbd tbd tbd tbd tb d tbd tbd tbd tbd % fs channel g ai n error temperature coefficient tbd tbd tbd tbd d %/ c gain matching tbd tbd tbd tbd (1) this is specified by design and characterization; it is not tested in production.
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 8 www.ti.com www.ti.com product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue th ese products without notice. electrical character istics t ypical values at 25c, min & max values are across the full temperature range t min = - 40c to t max = 85c, avdd = 3.3v, drvdd = 3.3 v, 50% clock duty cycle, - 1dbfs differential analog input, internal reference, applies to cmos & lvds interfaces, unless otherw ise noted. ads62p45 125 msps ads62p44 105 msps ads62p43 80 msps ads62p42 65 msps parameters min typ max min typ max min typ max min typ max unit dynamic characteristics fin= 10mhz 74.3 74.3 74.4 74.5 fin = 50mhz tbd 73. 8 73.8 tbd 74.1 74.2 fin = 70mhz 73.6 tbd 73.6 74 tbd 74.1 0 db gain 71.8 71.8 72.5 72.5 fin = 170mhz 3.5 db gain 71 71 71. 4 71. 4 0 db gain 7 1 7 1 72 72 sn r signal to noise ratio, cmos fin = 230mhz 3.5 db gain 70 70 71 71 dbfs fin= 10mhz 74.5 74.5 74.6 74.7 fin = 50mhz tbd 7 4 74 tbd 74.3 74.4 fin = 70mhz 73. 8 tbd 73.8 74.2 tbd 74.3 0 db gain 72.1 72.1 72.7 72.7 fin = 170mhz 3.5 db gain 71 71 71.8 71.8 0 db gain 71 .2 71 72.2 72.2 sn r signal to noise ratio, lvds fin = 230mhz 3.5 db gain 70. 1 70. 1 71. 2 71. 2 dbfs rms output noise inputs tied to common - mode 0.96 0.96 0.96 0.96 lsb
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 9 product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without no tice. w ww.ti.com www.ti.com electrical character istics typical values at 25c, min & ma x values are across the full temperature range t min = - 40c to t max = 85c, avdd = 3.3v, drvdd = 3.3 v, 50% clock duty cycle, - 1dbfs differential analog input, internal reference, applies to cmos & lvds interfaces, unless otherwise noted. ads62p45 125 msps ads62p44 105 msps ads62p43 80 msps ads62p42 65 msps parameters min typ max min typ max min typ max min typ max unit fin= 10mhz 73.8 73.8 73.9 74 fin = 50mhz tbd 73.2 73.2 tbd 73.6 73.7 fin = 70mhz 73 tbd 73 73.4 tbd 73.5 0 db gain 70.6 70.7 71.5 71.5 fin = 170mhz 3.5 db gain 70.1 70.2 70.6 70.6 0 db gain 68.7 68.7 69.7 69 .9 sinad signal to noise & distortion ratio, cmos fin = 230mhz 3.5 db gain 68.4 68.5 69.5 69.6 dbfs fin= 10mhz 74 74 74.1 74.1 fin = 50mhz tbd 73.4 73.4 tbd 73.8 73.8 fin = 70mhz 73.2 tbd 73.4 73.6 tbd 73.6 0 db gain 70.8 70.8 71.7 71.6 fin = 170mhz 3.5 db gain 70.5 70.5 70.8 70.7 0 db gain 68.9 68.9 68.1 68 sinad signal to noise & distortion ratio, lvds fin = 230mhz 3.5 db gain 68.6 68.7 69.7 69.7 dbfs enob , effective number of bits fin = 50 mhz tbd 11.8 11.8 tbd 11.9 1 2 lsb
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 10 www.ti.com www.ti.com product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue th ese products without notice. electrical character istics typical values at 25c, min & max val ues are across the full temperature range t min = - 40c to t max = 85c, avdd = 3.3v, drvdd = 3.3 v, 50% clock duty cycle, - 1dbfs differential analog input, internal reference, applies to cmos & lvds interfaces, unless otherwise noted. ads62p45 125 msps ads62p44 105 msps ads62p43 80 msps ads62p42 65 msps parameters min typ max min typ max min typ max min typ max unit fin= 10mhz 92 92 94 94 fin = 50mhz tbd 82 82 tbd 88 88 fin = 70mhz 85 tbd 86 86 tbd 86 0 db gain 79 80 81 82 fin = 170mhz 3.5 db gain 81 82 83 84 0 db gain 76 78 79 80 sfdr spurious free dynamic range fin = 230mhz 3.5 db gain 78 80 81 82 dbc fin= 10mhz 90 90 92 92 fin = 50mhz tbd 80.5 80.5 tbd 86 86 fin = 70mhz 83.5 tbd 84 84 tbd 84 0 db gain 76 77 78 79 fin = 170mhz 3.5 db gain 78 79 80 81 0 db gain 73 75 76 77 thd, total harmonic distortion fin = 230mhz 3.5 db gain 75 77 78 79 dbc
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 11 product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without no tice. w ww.ti.com www.ti.com electrical cha racteristics typical values at 25c, min & max values are across the full temperature range t min = - 40c to t max = 85c, avdd = 3.3v, drvdd = 3.3 v, 50% clock duty cycle, - 1dbfs differential analog input, internal reference, applies to cmos & lvds interfaces, unless otherwise noted. ads62p45 125 msps ads62p44 105 msps ads62p43 80 msps ads62p42 65 msps parameters min typ max min typ max min typ max min typ max unit fin= 10mhz 94 94 96 96 fin = 50mhz tbd 85 85 tbd 90 90 fin = 70mhz 88 tbd 88 88 tbd 88 0 db gain 79 80 81 82 fin = 170mhz 3.5 db gain 81 82 83 84 0 db gain 76 78 79 80 hd2 second harmonic distortion fin = 230mhz 3.5 db gain 78 80 81 82 dbc fin = 10mhz 92 92 94 94 fin = 50mhz tbd 82 82 tbd 88 88 fin = 70mhz 85 tbd 86 86 tbd 86 0 db gain 79 80 81 82 fin = 170mhz 3.5 db gain 81 82 83 84 0 db gain 76 78 79 80 hd3 third harmonic distortion fin = 230mhz 3.5 db gain 78 80 81 82 dbc
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 12 www.ti.com www.ti.com product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue th ese products without notice. electrical character istics typical values at 25c, min & max values are across the full temperature range t min = - 40c to t max = 85c, avdd = 3.3v, drvdd = 3.3 v, 50% clock duty cycle, - 1dbfs differential analog input, internal ref erence, applies to cmos & lvds interfaces, unless otherwise noted. ads62p45 125 msps ads62p44 105 msps ads62p43 80 msps ads62p42 65 msps parameters min typ max min typ max min typ max min typ max unit fin= 10mhz 96 96 98 98 fin = 50mhz 88 88 92 94 fin = 70mhz 91 91 91 91 fin = 170mhz 83 84 85 86 worst spur other than second , third harmonics fin = 230mhz 85 86 87 88 dbc imd 2 - tone intermodulation distortion f1 = 46 mhz, f2 = 50 mhz, each tone at - 7 dbf s 95 95 98 98 dbfs input overload recovery recovery to within 1% (of final value) for 6 - db overload with sine wave input 1 1 1 1 clock cycles cross - talk signal frequency = 10 mhz 100 100 100 100 db cross - talk cross - talk signal f requency = 50 mhz 95 95 95 95 db psrr ac power supply rejection ratio for 100 mv pp, 1mhz signal on avdd supply tbd tbd tbd tbd dbc
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 13 product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without no tice. w ww.ti.com www.ti.com digital characterist ics the dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1 . avdd=3.3v, drvdd=1.8v to 3.3v , unless otherwise specified. (1) lvds buffer current setting, i o = 3.5 ma (2) external differential load resistance between the lvds output pairs, r load = 50 ads62p45 / ads6 2p 44 / ads6 2p 43 / ads6 2p 42 parameter conditions min typ max unit digital inputs high - level input voltage 2.4 v low - level input voltage 0.8 v high - level input current 33 a low - level input current - 33 a input capacitance 4 pf digital outputs C cmos mode high - level output voltage drvdd v low - level output voltage 0 v output capacitance (in ternal to device) 2 pf digital outputs C lvds mode (1) (2) , drvdd = 3.3v high - level output voltage 1375 mv low - level output voltage 1025 mv output differential voltage, |v od | 350 mv v os output offset voltage common - mode voltage of outp a nd o utm 1200 mv output capacitance output capacitance inside the device, from either output to ground 2 pf
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 14 www.ti.com www.ti.com product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue th ese products without notice. timing characteristi cs C lvds and cmos modes (1) typical values at 25c, min and max values are across the full temperature ra nge t min = - 40c to tmax = 85c , avdd = 3.3v, drvdd = 1.8 v to 3.3v, 3.0 vpp sine wave input clock, c load = 5pf (2) , i o = 3.5ma , r load = 100 (3) , no internal termination, unless otherwise noted . ads62p45 ads62p44 ads62p43 ads62p42 parameter conditions min typ max min typ max min typ max min typ max unit t a , aperture delay tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns t j , aperture jitter 130 130 130 130 fs rms from power down global 15 15 15 15 s from channel standby 100 100 100 100 n s wake - up time from output buffer disable 100 100 100 100 ns default 14 14 14 14 clock cycles latency low latency mode 10 10 10 10 clock cycles ddr lvds interface ( 4) drvdd = 3.3v t su data setup time (5) data valid (6) to zero - crossing of clkoutp tbd 1.5 tbd 2.3 tbd 3.8 tbd 5.2 ns t h data hold time (5) zero - crossing of clkoutp to data becoming invalid (6) tbd 2.3 tbd 2.3 tbd 2.3 tbd 2.3 ns t pdi clock propagation delay input clock rising edge cross - over to output clock rising edge cross - over tbd 5.5 tbd tbd 5.5 tbd tbd 5.5 tbd tbd 5.5 tbd ns lvds bit clock duty cycle duty c ycle of diffe rential clock 50% 50% 50% 50% t rise, t fall data rise time, data fall time 110 110 110 110 ps t clkrise, t clkfall output clock rise time, output clock fall time rise time measured from - 100mv to +100mv , fall time measured from +100mv to - 100mv 120 120 120 120 ps
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 15 product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without no tice. w ww.ti.com www.ti.com ads62p45 ads62p44 ads62p43 ads62p42 parameter conditions min typ max min typ max min typ max min typ max unit parallel cmos interf ace , drvdd = 2.5v to 3.3v t su data setup time ( 5 ) data vali d ( 7 ) to zero - crossing of clkout tbd 3.5 tbd 4.3 tbd 5.8 tbd 7.2 ns t h data hold time ( 5 ) zero - crossing of clkout to data becoming invalid ( 7 ) tbd 3.2 tbd 4 tbd 5.5 tbd 7 ns t pdi clock propagation delay input clock rising edge cross - over to outp ut clock rising edge cross - over tbd 7.3 tbd tbd 7.3 tbd tbd 7.3 tbd tbd 7.3 tbd ns output clock duty cycle duty cycle of output clock, clkout 53 53 53 53 t rise, t fall data rise time, data fall time rise time measured from 20% to 80% of drvdd , f all time measured from 80% to 20% of drvdd 1.5 1.5 1.5 1.5 ns t clkrise, t clkfall output clock rise time, output clock fall time rise time measured from 20% to 80% of drvdd fall time measured from 80% to 20% of drvdd 1.5 1.5 1.5 1 .5 ns notes: 1. timing parameters are ensured by design and characterization and not tested in production. 2. c load is the effective external single - ended load capacitance between each output pin and ground 3. i o refers to the lvds buffer current setting; r load is the differential load resistance between the lvds output pair. 4. measurements are done with a transmission line of 100 characteristic impedance between the device and the load. 5. setup and hold time specifications take into account the effect of jitte r on the output data and clock. these specifications also assume that the data and clock paths are perfectly matched within the receiver. any mismatch in these paths within the receiver would appear as reduced timing margin. 6. data valid r efers to logic high of +100.0mv and logic low of - 100.0mv. 7. data valid refers to logic hig h of 2.0v and logic low of 0.8v for drvdd = 3.3v & logic hig h of 1.7v and logic low of 0.7v for drvdd = 2.5 v.
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 16 www.ti.com www.ti.com product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue th ese products without notice. o e o e o e o e o e o e o e o e o e o e n n - 1 n + 1 14 clock cycles * input clock clkoutm clkoutp output data dxp , dxm n - 10 n - 9 ddr lvds n - 10 n - 9 n - 1 n n + 1 n + 2 14 clock cycles * clkout output data d 0 - d 13 parallel cmos input signal sample n n + 1 n + 2 n + 3 n + 4 t h t pdi t a e C even bits d 0 , d 2 , d 4 , d 6 , d 8 , d 10 , d 12 o C odd bits d 1 , d 3 , d 5 , d 7 , d 9 , d 11 , d 13 t su t h t pdi clkm clkp n + 2 t su n + 14 n + 15 n + 16 * latency is 10 clock cycles in low latency mode figure 2 lat ency diagram
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 17 product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without no tice. w ww.ti.com www.ti.com figure 3 lvds mode timing figure 4 cmos mode timing
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 18 www.ti.com www.ti.com product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue th ese products without notice. device configuration ads62p4x can be configured independently using either parallel interface control or serial interface pr ogramming. using parallel interface control only to control the device using parallel interface, keep reset tied to high ( a vdd). p ins sen, sclk , ctrl1, ctrl2 and ctrl3 can be used to directly control certain functions of the adc. after power - up, the devi ce will automatically get configured as per the parallel pin voltage settings ( table 4 to table 6 ) . in this mode, sen and sclk function as parallel analog control pins , wh ich can be configured using a simple resistor divider as shown in figure 5 . the table below has a description of the modes controlled by the parallel pins. table 3 parallel pin definition co ntrol pin type of pin controls modes s clk co arse g ain and internal/ e xternal reference sen analog control pins ( controlled by analog voltage levels , see figure 5 ). lvds/cmos interface and output data format ctrl 1 ctrl2 ctrl3 digital control pin s (controlled by digital logic levels) together control various power down modes and mux mode. using serial interface programming only to program the device using the serial interface, keep reset low . pins sen, sda ta, and sclk function as serial interface digital pins and are used to access the internal registers of adc. the registers must first be reset to their default values either by applying a pulse on reset pin or setting bit = 1 . after r eset, the reset pin must be kept low . the serial interface section describes the register programming and register reset in more detail. since the parallel pins ( ctrl1, ctrl2, ctrl3 ) are not used in this mode, they must be tied to ground.
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 19 product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without no tice. w ww.ti.com www.ti.com using both serial in terfa ce and parallel cont rols for increased flexibility, a combination of serial interface registers and parallel pin controls (c trl1 to ctrl3 ) can also be used to configure the device. to allow this, keep reset low . the parallel interface control pins c trl1 to c trl3 are available. after power - up, the device will automatically get configured as per the voltage settings on these pins ( table 6 ). sen, sdata, and sclk function as serial interface digital pins and are used to access the internal registers of adc. the registers must first be reset to their default values either by applying a pulse on reset pin or by setting bit = 1 . after reset, the reset pin must be kept low . the s erial i nterface section describes the re gister programming and register reset in more detail. since the power down modes can be controlled using both the parallel pins and serial registers, the priority between the two is determined by bit. when bit = 0, pins ctrl1 to ctrl3 contro l the power down modes. with = 1, register bits control these modes, over - riding the pin settings. details of parallel configuration only the functions controlled by each parallel pin are described below. table 4 sclk (analog control pin ) sclk description 0 0db gain and internal reference (3/8) a vdd 0db gain and external reference (5/8) 2a vdd 3.5db coarse gain and external reference a vdd 3.5db coarse gain and internal reference table 5 sen (analog control pin ) sen description 0 2 s co mplem ent for ma t and ddr lvds output (3/8) a vdd straight binary and ddr lvds output (5/8) a vdd straight binary and parallel cmos output a vdd 2 s co mplem ent for ma t and parallel cmos output
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 20 www.ti.com www.ti.com product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue th ese products without notice. table 6 ctrl1, ctrl2 and ctrl3 (digital control pins) ctrl1 ctrl2 ctrl3 description low low low normal operation low low high channel a output buffer disabled low high low channel b output buffer disabled low high high channel a and b outp ut buffer disabled high low low power g lobal down high low high channel a standby high high low channel b standby high high high m ux mode of operation , channel a and b data is multiplexed and output on d b 13 to d b 0 pins. see multiplexed output mode for detailed description. figure 5 simple scheme to configure analog control pins (sclk, sen)
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 21 product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without no tice. w ww.ti.com www.ti.com serial interface the adc has a set of internal registers, which can be accessed by the serial interface formed by pins sen (serial int erface enable), sclk (serial interface clock) and sdata (serial interface data) . serial shift of bits into the device is enabled when sen is low. serial data sdata is latched at every falling edge of sclk when sen is active (low). the serial data is loade d into the register at every 16 th sclk falling edge when sen is low. in case the word length exceeds a multiple of 16 bits, the excess bits are ignored. data can be loaded in multiple of 16 - bit words within a single active sen pulse. the first 8 bits form the register address & the remaining 8 bits the register data. the interface can work with sclk frequency from 20 mhz down to very low speeds (few hertz) and also with non - 50% sclk duty cycle. register initialization after power - up, the internal registers must be initialized to their default values. this can be done in one of two ways C 1) either through hardware reset by applying a high - going pulse on reset pin (of width greater than 10ns) as shown in figure 6 or 2) by applying software reset. using the serial interface, set bit = 1 . this initializes internal registers to their default values and then self - resets the bit to low . in this case, keep reset pin low . figure 6 serial interface timing
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 22 www.ti.com www.ti.com product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue th ese products without notice. serial interface tim ing characteristics typical values at 25c, min and max values across the full temperature range t min = - 40c to t max = 85c, avdd = 3.3v, drvdd = 1.8v to 3.3v, unless otherwise noted. parameter m in typ max unit f sclk sclk frequency > dc 20 mhz t sloads sen to sclk setup time 25 n s t sloadh sclk to sen hold time 25 n s t ds sdata setup time 25 n s t dh sdata hold time 25 n s reset timing typical values at 25c, min and max values across the full temperature range t min = - 40c to t max = 85c, unless otherwise noted. parameter conditions min typ max unit t 1 power - on delay delay fro m power - up of avdd and drvdd to reset pulse active 5 m s t 2 reset pulse width pulse width of active reset si gnal 10 ns t 3 register write delay delay from reset disable to sen active 25 ns t po power - up time delay from power - up of avdd and drvdd to output stable 7 m s
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 23 product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without no tice. w ww.ti.com www.ti.com figure 7 reset timing diagram note: a high - going pulse on reset pin is required in serial interface mode in case of initialization through hardware reset. for parallel interface operation, reset has to be tied permanently high.
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 24 www.ti.com www.ti.com product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue th ese products without notice. serial register map table 7 summary of functions support ed by serial interface (1) (2) register address register functions a7 - a0 in hex d7 d6 d5 d4 d3 d2 d1 d0 00 0 0 0 0 0 0 software reset 0 10 0 0 0 0 0 0 11 0 0 lvds buffer current double lvds bu ffer current programmability 12 0 0 internal termination programmability 13 0 0 0 0 0 0 0 14 over - ride bit 0 < output interface > lvds or cmos interface 3.5 db gain [ int ernal / ext ernal reference 16 0 0 0 2s complement or straight binary bit/byte wise (lvds only) 17 0 0 0 0 0 to 6 db gain in 0.5 db steps 18 lower 8 bits 19 0 0 upper 6 bits 1a offset correction time constant 0 to 0.5 db, step s of 0.05 db 1b offset correction enable 0 < filter coeff select > in - built or custom coefficients enable decimation decimate by 2,4,8 1d 0 0 0 0 0 0 1e to 2f 12 coefficients, each 12 bit signed 1) multiple functions in a register can be programmed in a single write operation.
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ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 25 product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without no tice. w ww.ti.com www.ti.com descriptio n of serial register s a 7 - a0 (hex) d7 d6 d5 d4 d3 d2 d1 d0 00 0 0 0 0 0 0 software reset 0 d1 1 software reset applied C resets all internal registers and self - clears to 0. a 7 - a0 (hex) d7 d6 d5 d4 d3 d2 d1 d0 10 0 0 0 0 0 0 d7 - d6 output clock buffer drive strength control 01 weaker than default drive 00 default drive strength 1 1 stronger than default drive strength (recommended for load capacitances > 5 pf) 1 0 maximum drive strength (recommended for load capacitances > 5 pf) a 7 - a0 (hex) d7 d6 d5 d4 d3 d2 d1 d0 11 0 0 lvds buffer current double lvds buffer current programmability d1 - d0 output data buffer drive strength con trol 01 weaker than default drive 00 default drive strength 11 stronger than default drive strength (recommended for load capacitances > 5 pf) 10 maximum drive strength (recommended for load capacitances > 5 pf) d3 - d2 lvds current programma bility 00 3.5ma 01 2.5ma 10 4.5ma 11 1.75ma
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 26 www.ti.com www.ti.com product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue th ese products without notice. d5 - d4 lvds current double control 00 default current, set by 01 lvds clock buffer current is doubled, 2x 10 lvds data & clock buffers current are doubled, 2x 11 unused a 7 - a0 (hex) d7 d6 d5 d4 d3 d2 d1 d0 12 0 0 internal termination programmability d5 - d3 internal termination control for data outputs 000 no internal termination 001 300 010 180 011 110 100 150 101 100 110 81 111 60 d2 - d0 internal termination control for clock output 000 no internal termination 001 300 010 180 011 110 100 150 101 100 110 81 111 60
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 27 product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without no tice. w ww.ti.com www.ti.com a 7 - a0 (hex) d7 d6 d5 d4 d3 d2 d1 d0 13 0 0 0 0 0 0 0 d4 offset correction becomes inactive and the last estimated offset value is used to cancel the offset 0 offset correction active 1 offset correction inactive a 7 - a0 (hex) d7 d6 d5 d4 d3 d2 d1 d0 14 over - ride b it 0 < output interface > lvds or cmos interface 3.5 db gain [ int ernal / ext ernal reference d2 - d0 000 normal operation 001 channel a output buffer disabled 010 channel b output buffer disabled 011 ch annel a & b output buffers disabled 100 p ower down global 101 channel a standby 110 channel b standby 111 multiplexed mode , mux - (only with cmos interface) channel a and b data i s multiplexed and output on d b 13 to d b 0 pins. d3 ][ reference mode 0 inter nal reference enabled 1 external reference enabled d4 coarse gain control 0 0 db coarse gain 1 3.5 db coarse gain
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ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 28 www.ti.com www.ti.com product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue th ese products without notice. d5 < output interface > output interface selection 0 parallel cmos data outputs 1 ddr lvds data outputs d7 over - ride bit - the power down modes can also be controlled using parallel pins. by setting = 1, register bits will over - ride the settings of the parallel pins. 0 disable over - ride C pins ctrl1 to ctrl3 control power down modes. 1 enable over - ride - bits control power down modes. a 7 - a0 (hex) d7 d6 d5 d4 d3 d2 d1 d0 16 0 0 0 2s complement or straight binary bit / byte wise (lvds only) d2 - d0 test patterns to verify capt ure 000 normal adc operation 001 outputs all zeros 010 outputs all ones 011 outputs toggle pattern 100 outputs digital ramp 101 outputs custom pattern 110 unused 111 unused d3 bit - wise/byte - wise selection (ddr lvds mode only) 0 bit wise C even bits (d0, d 2, d4, d6, d8, d10, d12) on clkout rising edge and odd bits (d1, d3, d5, d7, d9, d11, d13) on clkout falling edge 1 byte wise C lower 7 bits (d0 - d 6 ) at clkout rising edge and upper 7 bits (d 7 - d13) at clkout falling edge d4 data format select ion 0 2s complement 1 straight binary
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 29 product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without no tice. w ww.ti.com www.ti.com a 7 - a0 (hex) d7 d6 d5 d4 d3 d2 d1 d0 17 0 0 0 0 0 to 6 db gain in 0.5 db steps d3 - d0 gain programmability in 0.5 db steps 0000 0 db gain, default after reset 0001 0.5 db gain 0010 1.0 db gain 0011 1.5 db gain 0100 2.0 db gain 0101 2.5 db gain 0110 3.0 db gain 0111 3.5 db gain 1000 4.0 db gain 1001 4.5 db gain 1010 5.0 db gain 1011 5.5 db gain 1100 6.0 db gain others unused a 7 - a0 (hex) d7 d6 d5 d4 d3 d2 d1 d0 18 lowe r 8 bits 19 0 0 upper 6 bits d7 - d0 8 lower bits of custom pattern available at the output instead of adc data. d5 - d0 6 upper bits of custom pattern available at the output instead of adc data
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 30 www.ti.com www.ti.com product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue th ese products without notice. a 7 - a0 (hex) d7 d6 d5 d4 d3 d2 d1 d0 1a offset correction time constant 0 to 0.5 db, steps of 0.05 db d3 - d0 enables fine gain correction in steps of 0.05 db (same correction applies to both channels ) 0000 0 db 0001 +0.05 db 0010 +0.10 db 0011 +0.15 db 0100 +0.20 db 0101 +0.25 db 0110 +0.30 db 0111 +0.35 db 1000 +0.40 db 1001 +0.45 db 1010 +0.5 db d6 - d4 , time constant of offset correction in number of clock cycles (seconds, for sampling f requency = 125msps) 000 2 27 (1.1 s) 001 2 26 (0.55 s) 010 2 25 (0.27 s) 011 2 24 (0.13 s) 100 2 28 (2.15 s) 101 2 29 (4.3 s) 110 2 27 (1.1 s) 111 2 27 (1.1 s) d7 0 default latency, 1 4 clock cycles 1 low latency enabled, 10 clock cycles - digital processing block is bypassed.
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 31 product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without no tice. w ww.ti.com www.ti.com a 7 - a0 (hex) d7 d6 d5 d4 d3 d2 d1 d0 1b offset correction enable 0 in - built or custom coefficients enable decimation decimat e by 2,4,8 d2 - d0 000 decimate by 2 (pre - defined or user coefficients can be used) 001 decimate by 4 (pre - defined or user coefficients can be used) 011 no decimation (pre - defined coefficients are disabled, only custom coefficients are av ailable ) 100 decimate by 8 (only custom coefficients are available) d3 0 even taps enabled (24 coefficients) 1 odd taps enabled (2 3 coefficients) d4 0 decimation disabled 1 decimation enabled d5 0 pre - de fined coefficients are loaded in the filter 1 user - defined coefficients are loaded in the filter (coefficients have to be loaded in registers C to - ) d7 0 offset correction disabled 1 offset correction enabled
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 32 www.ti.com www.ti.com product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue th ese products without notice. a 7 - a0 (hex) d7 d 6 d5 d4 d3 d2 d1 d0 1d 0 0 0 0 0 0 d1 - d0 with decimate by 2 , = 000: 00 low pass filter ( - 6 db frequency at fs/4) 01 high p ass filter ( - 6 db frequency at fs/4) 10,11 unused with decimate by 4 , = 001: 00 low pass filter ( - 3 db frequency at fs/8) 01 band pass filter ( center frequency at 3 fs/ 16 ) 10 band pass filter (center frequency at 5 fs/16) 11 high pass filter ( - 3 db frequency at 3fs/8) a7 - a0 ( hex ) d7 d6 d5 d4 d3 d2 d1 d0 1e to 2f custom fir coefficients see table 14
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 33 product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without no tice. w ww.ti.com www.ti.com pin description (cmo s interface )
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 34 www.ti.com www.ti.com product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue th ese products without notice. pin a ssignments (cmos int erface ) pin name description pin number number of pins avdd analog po wer supply agnd analog ground clkp, clkm differential input clock inp_a, inm_a differential input signal C channel a inp_b, inm_b differential input signal C channel b vcm internal reference mode C common - mode voltage output. external refere nce mode C reference input. the voltage forced on this pin sets the adc internal references. reset serial interface reset input. in serial interface mode, th e user must initialize internal registers through hardware reset by applying a high - goin g pulse on this pin or by using software reset (refer to serial interface section). in parallel interface mode , the user has to tie reset pin permanently high. ( sclk, sdata and sen are used as parallel pin controls in this mode) the pin has an internal 100k pull - down resistor. sclk this pin functions as serial interface clock input when reset is low . it functions as analog control pin when reset is tied high & controls c oarse gain and internal / e xternal reference selection . see table 4 for details. this pin has an internal pull - down resistor to ground. sdata this pin functions as serial interface data input when reset is low. this pin has an internal pull - down resistor to ground. sen this pin functions as seri al interface enable input when reset is low . it functions as analog control pin when reset is tied high & controls the output interface (lv ds/cmos) and data format selection . see table 5 for details. this pin has a n internal pull - up resistor to avdd. ctrl1 ctrl2 ctrl3 these are digital logic input pins. t hey control various power down and m ultiplexed mode. see table 6 for details. d a13 to d a0 channel a 14 - bit d ata outputs, cmos db13 to db0 channel b 14 - bit data outputs, cmos clkout cmos output clock drvdd digital supply drgnd digital ground pad digital ground. solder the pad to the digital ground on the board using m ultiple vias
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 35 product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without no tice. w ww.ti.com www.ti.com for good electrica l & thermal performance. nc do not connect
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 36 www.ti.com www.ti.com product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue th ese products without notice. pin description ( l vds interface )
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 37 product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without no tice. w ww.ti.com www.ti.com pin assignments (lvd s interface ) pin name description pin number number of pins avdd analog power supply agnd analog ground clkp, clkm differential input clock inp_a, inm_a differential input signal C channel a inp_b, inm_b differential input signal C channel b vcm internal reference mode C common - mode voltage output. external reference mode C reference input. the voltage forced on this pin s ets the adc internal references. reset serial interface reset input. in serial interface mode, th e user must initialize internal registers through hardware reset by applying a high - goin g pulse on this pin or by using software reset (refer to serial int erface section). in parallel interface mode , the user has to tie reset pin permanently high. ( sclk, sdata and sen are used as parallel pin controls in this mode) the pin has an internal 100k pull - down resistor. sclk this pin functions as serial interface clock input when reset is low . it functions as analog control pin when reset is tied high & controls coarse gain and internal/external reference selection. see table 4 for details. this pin has an internal pull - down resistor to ground. sdata this pin functions as serial interface data input when reset is low. this pin has an internal pull - down resistor to ground. sen this pin functions as seri al interface enable input when reset is low . it functions as analog control pin when reset is tied high & controls the output interface (lvds/cmos) and data format selection. see table 5 for details. this pin has a n internal pull - up resistor to avdd. ctrl1 ctrl2 ctrl3 these are digital logic input pins. together they control various power down and multiplexed mode. see table 6 for details. nc do not connect
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 38 www.ti.com www.ti.com product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue th ese products without notice. pin name description pin number number of pins da0p channel a differential output data d0 & d1, true da0m channel a differential output data d0 & d1 , complement da2p channel a differential output data d2 & d3 , true da2m channel a different ial output data d2 & d3 , complement da4p channel a differential output data d4 & d5 , true da4m channel a differential output data d4 & d5 , complement da6p channel a differential output data d6 & d7 , true da6m channel a differential output d ata d6 & d7 , complement da8p channel a differential output data d8 & d9 , true da8m channel a differential output data d8 & d9 , complement da10p channel a differential output data d10 & d11 , true da10m channel a differential output data d10 & d11 , complement da12p channel a differential output data d1 2 & d1 3 , true da12m channel a differential output data d1 2 & d1 3 , complement clkoutp differential output clock, true clkoutm differential output clock, complement db0p channel b differential output da ta d0 & d1 , true db0m channel b differential output da ta d0 & d1 , complement db2p channel b differential output da ta d2 & d3 , true db2m channel b differential output da ta d2 & d3 , complement db4p channel b different ial output da ta d4 & d5 , true db4m channel b differential output da ta d4 & d5 , complement db6p channel b differential output da ta d6 & d7 , true db6m channel b differential output da ta d6 & d7 , complement db8p channel b differential output d a ta d8 & d9 , true db8m channel b differential output da ta d8 & d9 , complement db10p channel b differential output da ta d10 & d11 , true db10m channel b differential output da ta d10 & d11 , complement db 12p channel b differential output data d 1 2 & d1 3 , true db 12m channel b differential output data d1 2 & d1 3 , complement drvdd digital supply drgnd digital ground pad digital ground. solder the pad to the digital ground on the board using multiple vias for good electrical & thermal pe rformance.
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 39 product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without no tice. w ww.ti.com www.ti.com application information theory of operation ads62p4x is a low power 1 4 bit dual channel pipeline adc family fabricated in a cmos process using switched capaci tor techniques. the conversion process is initiated by a ris ing edge of the extern al input clock. once the signal is captured by the input sample & hold , the input sample is sequentially converted by a series of small resolution stages, with the outputs combined in a digital correction logic block. at every clock edge the sample propaga te s through the pipeline result ing in a data latency of 1 4 clock cycles . t he output is available as 14 - bit data , in ddr lvds or cmos and coded in either straight offset binary or binary 2 s complement format. analog input the analog input consists of a swi tched - capacitor based differential sample and hold architecture. this differential topology results in very good ac performance even for high input frequencies at high sampling rates. the inp and inm pins have to be externally biased around a common - mode v oltage of 1.5v , available on vcm pin 13. for a full - scale differential input, each input pin inp, inm has to swing symmetrically between vcm + 0.5v and vcm - 0.5v, resulting in a 2vpp differential input swing. the maximum swing is determined by the interna l reference voltages refp (2.5v nominal) and refm (0.5v, nominal). inp inm 25 e cbond ~ 1 pf csamp 4 . 0 pf rcr filter sampling capacitor sampling switch sampling switch ron 15 e ron 15 e csamp 4 . 0 pf 25 e 50 e 50 e 3 . 2 pf cpar 1 0 . 8 pf lpkg ~ 2 nh cbond ~ 1 pf resr 100 e resr 100 e cpar 2 1 pf cpar 2 1 pf sampling capacitor ron 10 e lpkg ~ 2 nh figure 8 analog input equivalent circuit
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 40 www.ti.com www.ti.com product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue th ese products without notice. the input sampling circuit has a high 3 - db bandwidth that extends up to 450 mhz (measured from the input pins to the s ampled voltage ) . tbd figure 9 adc analog bandwidth drive circuit requirements for optimum performance, the analog inputs must be driven differentially. this improves the common - mode noise immunity and even order harmonic rejection . a 5 resistor in series with each input pin is recommended to damp out ringing caused by the package parasitics. it is also necessary to present low impedance (< 50 ) for the common mode switching currents. t his can be achieved by using two resistors from each input terminated to the common mode voltage (vcm). in addition to the above, the drive circuit may have to be designed to provide a low insertion loss over the desired frequency range and matched impedance to the source. while doing this, the ad c input impedance must be considered. figure 10 & figure 11 show the impedance (zin = rin || c in) l ooking into the adc input pins . 0.0 0.1 1.0 10.0 100.0 0 100 200 300 400 500 600 frequency,mhz resistance, kohms figure 10 adc analog input resistance ( rin ) across frequency
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 41 product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without no tice. w ww.ti.com www.ti.com 0 1 2 3 4 5 6 7 8 9 0 100 200 300 400 500 600 frequency, mhz capacitance, pf figure 11 adc analog input capacitance ( cin ) across frequency using rf - transformer based drive circuits figure 12 shows a configurati on using a single 1:1 turns ratio transformer (for example, coilcraft wbc1 - 1) that can be used for low input frequencies (about 100 mhz). the single - ended signal is fed to the primary winding of the rf transformer. the transformer is terminated on the seco ndary side. putting the termination on the secondary side helps to shield the kickbacks caused by the sampling circuit from the rf transformer s leakage inductances. the termination is accomplished by two resistors connected in series, with the center poin t connected to the 1.5 v common mode (vcm pin). the value of the t ermination resistors (connected to common mode) has to be low (< 100 ) to provide a low - impedance path for the ad c common - mode switching currents.
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 42 www.ti.com www.ti.com product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue th ese products without notice. figure 12 drive circuit at low input frequencies at high input frequencies, the mismatch in the transformer parasitic capacitance (between the wind ings) results in degraded even - order harmonic performance. connecting two identical rf transformers back - to - back helps minimize this mismatch, and good performance is obtained for high frequency input signals. figure 13 shows an example using two transformers (coilcraft wbc1 - 1). an additional termination resistor pair (enclosed within the shaded box) may be required between the two transformers to improve the balance between the p and m sides. the center point of th is termination must be connected to ground. figure 13 drive circuit at high input frequencies
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 43 product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without no tice. w ww.ti.com www.ti.com using differential amplifier drive circuits figure 14 shows a drive circuit using a differential amplifier (ti's ths4509) to convert a single - ended input to differential output that can be interface to the adc analog input pins. in addition to the single - ended to differential conversion, the amplifier also provides gain (10 db). r fil helps to isolate the ampli fier outputs from the switching input of the adc. together with c fil it also forms a low - pass filter that band - limits the noise (and signal) at the adc input. as the amplifier output is ac - coupled, the common - mode voltage of the adc input pins is set using two 200 w resistors connected to vcm. the amplifier output can also be dc - coupled. using the output common - mode control of the ths4509, the adc input pins can be biased to 1.5 v. in this case, use +4 v and - 1 v supplies for the ths4509 so that its output common - mode voltage (1.5 v) is at mid - supply. 10 uf 0 . 1 uf 10 uf 0 . 1 uf r f r f r g r g 0 . 1 uf 0 . 1 uf r s r t + v s - v s cm r fil r fil c fil c fil 5 e 5 e inp inm ths 4509 vcm r s || r t 200 e 200 e 0 . 1 uf 500 e 500 e 0 . 1 uf 0 . 1 uf 0 . 1 uf figure 14 drive circuit using the ths4509 input common - mode to ensure a low - noise common - mode reference, the vcm pin is filtered with a 0.1uf low - inductance capacitor connected to g round. the vcm pin is designed to directly drive the adc inputs. each input pin of the adc sinks a common - mode current, about 165 ua (at 125msps). equation 1 describes the dependency of the common - mode current and the sampling frequency. msps 125 axfs 165 m equation 1 this equation helps to design the output capability and impedance of the cm driving circuit accordingly.
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 44 www.ti.com www.ti.com product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue th ese products without notice. reference ads62p4x has built - in internal reference s refp and refm, requiring no external components. d esign schemes are used to lineari z e the converter load seen by the reference s; this and the on - chip integration of the requisite reference cap acitors eliminates the need for external decoupling. the full - scale inpu t range of the converter can be controlled in the external reference mode as explained below. the internal or external reference modes can be selected by programming the serial interface register bit [ . figure 15 reference s ection internal reference when the device is in internal reference mode, the refp and refm voltages are generated internally . common - mode voltage (1.5v nominal) is output on vcm pin , which can be used to externally bias the analog input pins. external ref erence when the device is in external reference mode, the vcm acts as a reference input pin. t he voltage forced on the vcm pin is buffered and gained by 1.33 internally, generating the refp and refm voltages. the differential input voltage corresponding to full - scale is given by equation 2 . full - scale differential input pp = (voltage forced on vcm ) x 1.33 equation 2 in this mode, the 1.5v common - mode voltage to bias the input pins has to be generated externally.
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ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 45 product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without no tice. w ww.ti.com www.ti.com coarse gain and prog rammable fine gain ads62p4x includes gain settings that can be used to get improved sfdr performance (over 0db gain mode). for each gain setting, the analog input full - scale range scales proportionally, as s hown in table 8 . the coarse gain is a fixed setting of 3.5 db and is designed to improve sfdr with little degradation in snr. the fine gain is programmable in 0.5 db steps from 0 to 6 db; however the sfdr improve ment is achieved at the expense of snr. so, the programmable fine gain makes it possible to trade - off between sfdr and snr. the coarse gain makes it possible to get best sfdr but without losing snr significantly. the gains can be programmed using the seria l interface (bits and ) . note that the default gain after reset is 0db. table 8 full - scale range across gains gain, db type full - scale, vpp 0 default after reset 2v 3.5 coarse (fixed) 1.34 0.5 1.89 1.0 1.78 1.5 1.68 2 .0 1.59 2.5 1.50 3 .0 1.42 3.5 1.34 4 .0 1.26 4.5 1.19 5 .0 1.12 5.5 1.06 6 .0 fine (progr ammable) 1.00
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 46 www.ti.com www.ti.com product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue th ese products without notice. clock input the clock inputs can be driven differentially (sine, lvpecl or lvds) or single - ended (lvcmos), with litt le or no difference in performance between them. the common - mode voltage of the clock inputs is set to vcm using internal 5 k resistors as shown in figure 16 . this allows using transformer - coupled drive circuits for sine wave clock or ac - coupling for lvpecl, lvds clock sources ( figure 18 and figure 19 ). clkp 5 k e vcm 5 k e 6 pf 10 e 10 e lpkg ~ 2 nh cbond ~ 1 pf lpkg ~ 2 nh cbond ~ 1 pf resr ~ 100 e resr ~ 100 e clkm clock buffer ceq ceq ceq ~ 1 to 3 pf , equivalent input capacitance of clock buffer figure 16 internal clock buffer tbd figure 17 clock input impedance
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 47 product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without no tice. w ww.ti.com www.ti.com figure 18 differential clock driving circuit single - ended cmos clock can be ac - coupled to the clkp input, with c lkm (pin 11) connected to ground with a 0.1 - f capacitor, as shown in figure 19 . figure 19 single - ended clock driving circuit for best performance, the clock inputs have to be driven di fferentially, reducing susceptibility to common - mode noise. for high input frequency sampling, it is recommended to use a clock source with very low jitter. bandpass filtering of the clock source can help reduce the effect of jitter. there is no change in performance with a non - 50% duty cycle clock input.
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 48 www.ti.com www.ti.com product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue th ese products without notice. power down ads62p4x has three power down modes C power down global, channel standby and individual channel output buffer disable. these can be set using either the serial register bits or using the co ntrol pins ctrl1 to ctrl3. configure using parallel control pins power down modes serial interface ctrl1 ctrl2 ctrl3 total power, mw (1) wake - up time normal operation 000 low low low 792 - channel a output buffer disabled 001 low low high 782 fast ( 100 n s) channel b output buffer disabled 010 low high low 782 fast ( 100 n s) channel a & b output buffer disabled 011 low high high 772 fast ( 100 n s) power down global 100 high low low 50 slow ( 15 s ) channel a standby 101 high low high 482 fast ( 100 n s) channel b standby 110 high high low 482 fast ( 100 n s) multiplexed (mux) mode C output data of channel a & b is multiplexed & available on d b 13 to d b 0 pins. 111 high high high - - 1. sampling freque ncy = 125 msps, drvdd = 1.8v power down global in this mode, the entire chip including both the a/d converters, internal reference and the output buffers are powered down resulting in reduced total power dissipation of about 50 mw. the output buffers are i n high impedance state. the wake - up time from the global power down to data becoming valid in normal mode is typically 15 s. channel standby (individual or both channels) this mode allows the ind ividua l adcs to be powered down. t he internal references are active & this results in fast wake - up time, about 100 ns. the total power dissipation in standby is about 482 mw . outpu t b uffer d isable (individual or both channels) each channel s output buffer can be disabled & put in high impedance state . w akeup time is fast, about 100 ns. input clock stop in addition to the above, the converter enters a low - power mode when the input cl ock frequency falls below 1 msps. the power dissipation is about 140 mw. power supply sequenc e during power - up, the avdd and dr vdd supplies can come up in any sequence. the two supplies are separated i n the device. externally, they can be driven from sepa rate supplies or from a single supply.
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 49 product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without no tice. w ww.ti.com www.ti.com digital output infor mation ads62p4x provides 14 bit data per channel and a common output clock synchronized with the data. the output interface can be either parallel cmos or ddr lvds voltage levels and can be selec ted using serial register bit < output interface > or parallel pin sen. parallel cmos interface in the cmos mode, the output buffer supply (drvdd) can be operated over a wide range from 1.8 v to 3.3 v (typical). each data bit is output on separate pin as cm os v oltage level, every clock cycle ( figure 20 ). for drvdd > 2.2 v, it is recommended to use the cmos output clock (clkout) to latch data in the receiving chip. the rising edge of clkout can be used to latch data in the receiver, even at the highest sampling speed. it is r ecommended to minimize the load capacitance seen by data and clock output pins by using short traces to the receiver. also, match the output data and clock traces to minimize the skew between them. for drvdd < 2.2 v, it is recommended to use external clock (for example, input clock delayed to get desired s etup / hold times). da 0 da 1 da 2 da 3 da 12 da 13 clkout cmos output buffers 14 bit channel a data db 0 db 1 db 2 db 3 db 12 db 13 14 bit channel b data figure 20 cmos output interface
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 50 www.ti.com www.ti.com product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue th ese products without notice. output buffer strength programmability switching noise (caused by cmos output da ta transitions) can couple into the analog inputs during the instant of sampling and degrade the snr. the coupling and snr degradation increases as the output buffer drive is made stronger. to minimize this, ads6 2p4 x cmos output buffers are designed with c ontrolled drive strength to get best snr. the default drive strength also ensures wide data stable window for load capacitances up to 5 pf and drvdd supply voltage > 2.2 v. to ensure wide data stable window for load capacitance > 5 pf, there exists option to increase the output data & clock drive strength s using the serial interface ( < dataout strength> & ). note that for drvdd supply voltage < 2.2 v, it is recommended to use maximum drive strength (for any value of load capacitance). cmos interface power dissipation with cmos outputs, the drvdd current scales with the sampling frequency and the load capacitance on every output pin. the maximum drvdd current occurs when each output bit toggles between 0 and 1 every clock cycle. in actual app lications, this condition is unlikely to occur. the actual drvdd current would be determined by the average number of output bits switching, which is a function of the sampling frequency and the nature of the analog input signal. digital current due to cm os output switching = c l x drvdd x (n x f avg ) , where c l = load capacitance, n x f avg = average number of output bits switching . figure tbd shows the current with various load capacitances across sampling frequencies at 2 mhz analog input frequency.
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 51 product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without no tice. w ww.ti.com www.ti.com ddr lvds interface the lvds interface works only with 3.3v drvdd supply. in this mode, the 14 data bits of each channel and a common output clock are available as lvds (low voltage differential signal) levels. two successive data bits are multiplexed and outp ut on each lvds differential pair every clock cycle (ddr - double data rate, figure 22 ). clkoutp clkoutm da 0 p da 0 m da 2 p da 2 m output clock data bits d 0 , d 1 data bits d 2 , d 3 pins da 12 p da 12 m data bits d 12 , d 13 14 bit channel a data lvds buffers db 0 p db 0 m db 2 p db 2 m data bits d 0 , d 1 data bits d 2 , d 3 db 12 p db 12 m data bits d 12 , d 13 14 bit channel b data figure 21 ddr lvds outputs even data bits d0, d2, d4, d6, d8, d10 and d12 are output at the risi ng edge of clkoutp and the odd data bits d1, d3, d5, d7, d9, d11 and d13 are output at the fall ing edge of clkoutp. both the rising and falling edges of clkoutp have to be used to capture all the data bits.
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 52 www.ti.com www.ti.com product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue th ese products without notice. figure 22 ddr lvds interface lvds buffer current programmability the default lvds buffer output current is 3.5 ma. when terminated by 100 , this results in a 350 - mv single - ended voltage swing (700 - mvpp differential swing). the lvds buffer currents can also be p rogrammed to 2.5 ma, 4.5 ma, and 1.75 ma ( ). in addition, there exists a current double mode, where this current is doubled for the data and output clock buffers (register bits ).
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 53 product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without no tice. w ww.ti.com www.ti.com lvds buffer internal termination an internal termination option is available (using the serial interface), by which the lvds buffers are differentially terminated inside the device. the termination resistances available are C 300 , 185 , and 150 (nominal with 20% variation). any combination of these three terminations can be programmed; the effective termination is the parallel combination of the selected resistances. this results in eight effective terminations from open (no termination) to 6 0 . the internal termination helps to absorb any reflections coming from the receiver end, improving the signal integrity. with 100 internal and 100 external termination, the voltage swing at the receiver end is halved (compared to n o internal termination). the voltage swing can be restored by using the lvds current double mode. figure 2 3 & tbd figure 24 compare the lvds eye diagrams without and with 100 internal termination. with internal termination, the eye looks clean even with 10 pf load capacitance (from each out put pin to ground). the terminations can be programmed using register bits < lvds termination > . tbd figure 23 lvd s eye diagram C no internal termination tbd figure 24 lvds eye diagram C with 100 internal termination output d ata f ormat two output data formats are supported C 2s complement and straight binary. they can be selected using the serial interface register bit or controlling the sen pin in parallel configuration mode. in the event of an input voltage overdrive, the digital outputs go to the appropriate full scale level. for a positive overdrive, the output code is 0x 3 f ff in offset binary output format, and 0x 1f f f in 2s complement output format. for a negative input overdrive, the output code is 0x 0 000 in offset binary output format and 0x 20 00 in 2s complement output format.
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 54 www.ti.com www.ti.com product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue th ese products without notice. multiplexed output mode this mode is avail able only with cmos interface. in this mode, the digital outputs of both the channels are multiplexed and output on a single bus (da0 - da13 pins), as per the timing diagram shown in figure 25 . the channel b output pins (db0 - db13) a re tri - stated. since the output data rate on the d b bus is effectively doubled, this mode is recommended only for low sampling frequencies (< 65 msps). this mode can be enabled using register bits or u sing the parallel pins ctrl1 - 3 (). sample n sample n clkout clkout db 0 db 0 da 0 db 0 sample n + 1 sample n + 1 da 0 db 0 db 1 db 1 da 1 db 1 da 1 db 1 db 2 db 2 da 2 db 2 da 2 db 2 db 13 db 13 da 13 db 13 da 13 db 13 figure 25 multiplexed mode - output timing low latency mode the default latency of ads62p4x is 1 4 clock cycles. for applications, which cannot tolerate large latency, ads62p4x includes a special mode with 10 clock cycles latenc y. in the low latency condition, the digital processing block is bypassed and its features (offset correction, fine gain, decimation filters) are not available.
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 55 product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without no tice. w ww.ti.com www.ti.com details of the digit al processing block offset estimation block 24 tap filter - low pass - high pass - band pass decimation by 2 / 4 / 8 disable offset correction freeze offset correction 0 fine gain ( 0 to 6 db 0 . 5 db steps ) gain correction ( 0 . 05 db steps ) bypass decimation bypass filter to output buffers lvds or cmos 14 bits 14 bits 14 bits 14 bits filter select clipper digital processing block offset correction fine gain gain correction digital filter & decimation from adc output 14 bits 14 bits figure 26 digital proces sing block diagram several common digital processing functions have been integrated in the device C offset correction, fine gain, gain correction decimation & digital filters. by default after reset, the digital processing block is bypassed & all its funct ions are disabled. offset correction ads62p4x has an internal offset correction algorithm that estimates and corrects dc offset up to +/ - 10mv. the correction can be enabled using the serial register bit . once enabled, the algorithm estima t es the channel offset and applies the correction every clock cycle. the time constant of the correction loop is a function of the sampling clock frequency. the time constant can be controlled using register bit s as described in table 9 . it is also possible to freeze the offset correction using the serial interface ( ). once frozen, the offset estimation becomes inactive and the last estimated value is used for correction every cl ock cycle. note that the offset correction is disabled by default after reset. figure 27 shows the time response of the offset correction algorithm, after it is enabled.
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 56 www.ti.com www.ti.com product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue th ese products without notice. table 9 time constant of offs et correction algorithm d6 - d5 - d4 time constant (tc clk ) , number of clock cycles time constant, sec (=tc clk x 1/fs) (1) 000 2 27 1.1 001 2 26 0.55 010 2 25 0.27 011 2 24 0.13 100 2 28 2.15 101 2 29 4.3 110 2 27 1.1 111 2 27 1.1 (1) samp ling frequency, fs = 125 msps tbd figure 27 time response of offset correction gain correction ads62p4x includes option to make fine corrections to the adc channel gain. the corrections ca n be done in steps of 0.05 db , up to a max imum of 0.5 db, using the register bits . only positive corrections are supported and the same correction applies to both the channels. table 10 gain correction values d3 - d2 - d1 - d0 amount of correct ion, db 0000 0 0001 +0.05 0010 +0.1 0011 +0.15 0100 +0.20 0101 +0.25 0110 +0.30 0111 +0.35 1000 +0.40 1001 +0.45 1010 +0.5 other combinations unused
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 57 product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without no tice. w ww.ti.com www.ti.com decimation filter ads62p4x includes option to decimate the adc output data with in - built low pass, high pass or band pass filters. t he decimation rates & the type of filter can be selected using register bits & < decimation filter type > . decimation rates of 2, 4 or 8 are available and either low pass, high pass or band pass filt ers can be selected ( table 11 ) . by default, the decimation filter is disabled - use register bit to enable it. table 11 decimation filter m odes (1) combination of decimat ion rates & filter types serial interface settings decimation type of filter in - built low pass filter (pass band = 0 to fs/4) 0 0 0 0 0 0 1 decimate by 2 in - built high pass filter (pass band = fs/4 to fs/2) 0 0 0 0 1 0 1 in - built low pass filter (pass band = 0 to fs/8) 0 0 1 0 0 0 1 in - built 2 nd ban d pass filter (pass band = fs/8 to fs/4) 0 0 1 0 1 0 1 decimate by 4 in - built 3rd band pass filter (pass band = fs/4 to 3fs/8) 0 0 1 1 0 0 1 decimate by 4 in - built last band pass filter (pass band = 3fs/8 to fs/2) 0 0 1 1 1 0 1 decimate by 2 custom filter ( user programmable coefficients) 0 0 0 x x 1 1 decimate by 4 custom filter ( user programmable coefficients) 0 0 1 x x 1 1 decimate by 8 custom filter ( user programmable coefficients) 1 0 0 x x 1 1 no decimation custom filter ( user programmable coefficients) 0 1 1 x x 1 0
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 58 www.ti.com www.ti.com product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue th ese products without notice. decimation f ilter equation the decimation filter is implemented as 24 - tap fir with symmetrical coefficients (each coefficient is 12 - bit signed ). the filter equa tion is : ( ) 23) - x(n h0 22) - x(n h1 12) - x(n h11 11) - x(n h11 2) - x(n h2 1) - x(n h1 (n) x h0 2 1 ) n ( y 11 + + ? + + + ? + + + ? ? ? ? ? = by setting the register bit = 1, a 23 - tap fir is implemented: ( ) 22 - x(n h0 21) - x(n h1 12) - x(n h10 11) - x(n h11 10) - x(n h10 2) - x(n h2 1) - x(n h1 (n) x h0 2 1 ) n ( y 11 + + ? + + + + ? + + + ? ? ? ? ? = in the above equations, h0, h1 h11 are 12 bit signed representation of the coefficients, x(n) is the input data seque nce to the filter & y(n) is the filter output sequence. pre - define d coefficients the in - built filter types (low pass, high pass & band pass) use pre - defined coefficients . the frequency response of the in - built filters is shown in figure 28 & figure 29 . tbd figure 28 decimate by 2 filter response tbd figure 29 decimate by 4 filter response
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 59 product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without no tice. w ww.ti.com www.ti.com table 12 pre - defined coefficients for decimate by 2 filter s decimate by 2 coefficients low pass filter high pass filter h0 23 - 22 h1 - 37 - 65 h2 - 6 - 52 h3 68 30 h4 - 36 66 h5 - 61 - 35 h6 35 - 107 h7 118 38 h8 - 100 202 h9 - 197 - 41 h10 273 - 644 h11 943 106 1 table 13 pre - defined coefficients for decimate by 4 filters decimate by 4 coefficients low pass filter 1 st band - pass filter 2 nd band - pass filter high pass filter h0 - 17 - 7 - 34 32 h1 - 50 19 - 34 - 15 h2 71 - 47 - 101 - 95 h3 46 127 43 22 h4 24 73 58 - 8 h5 - 42 0 - 28 - 81 h6 - 100 86 - 5 106 h7 - 97 117 - 179 - 62 h8 8 - 190 294 - 97 h9 202 - 464 86 310 h10 414 - 113 - 563 - 501 h11 554 526 352 575
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 60 www.ti.com www.ti.com product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue th ese products without notice. custom filter coefficients with decimation t he filter coefficients can also be prog rammed by the user (custom). f or custom coefficient s, set the register bit & load the coefficients (h0 to h11) in registers 1e to 2f using the serial interface ( table 14 ) as: regi ster content = 1 2 bit signed representation of [ real coefficient value x 2 11 ] custom filter coefficients without decimation the filter with custom coefficients can also be used with the decimation mode disabled. in this mode, the filt er implementation is 12 - tap fir: ( ) 11) - x(n h6 10) - x(n h7 6) - x(n h11 5) - x(n h11 2) - x(n h8 1) - x(n h7 (n) x h6 2 1 ) n ( y 11 + + ? + + + ? + + + ? ? ? ? ? = table 14 register map for c ustom fir coefficients register address register functions a7 - a0 in hex d7 d6 d5 d4 d3 d2 d1 d0 1e coefficient h 0 <7:0> 1f coefficient h 1 <3:0> coefficient h 0 <1 1:8> 20 coefficient h 1 <11:4> 21 coefficient h 2 <7:0> 22 coefficient h 3 <3:0> coefficient h 2 <11:8> 23 coefficient h 3 <11:4> 24 coeff icient h 4 <7:0> 25 coefficient h 5 <3:0> coefficient h 4 <11:8> 26 coefficient h 5 <11:4> 27 coefficient h 6 <7:0 > 28 coefficient h 7 <3:0> coefficient h 6 <11:8> 29 coefficient h 7 <11:4> 2a coefficient h 8 <7:0> 2b coefficient h9 < 3:0> coefficient h 8 <11:8> 2c coefficient h 9 <11:4> 2d coefficient h 10 <7:0> 2e coefficient h 11 <3:0> coefficient h 10 <11:8> 2f coefficient h 11 <11:4>
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 61 product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without no tice. w ww.ti.com www.ti.com
ads62p45, ads62p44 ads62p43, ads62p42 rev1p0 sep 2007 62 www.ti.com www.ti.com product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue th ese products without notice. package information
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) ads62p42irgcr preview qfn rgc 64 2500 tbd call ti call ti ads62p42irgct preview qfn rgc 64 250 tbd call ti call ti ads62p43irgcr preview qfn rgc 64 2500 tbd call ti call ti ads62p43irgct preview qfn rgc 64 250 tbd call ti call ti ads62p44irgcr preview qfn rgc 64 2500 tbd call ti call ti ads62p44irgct preview qfn rgc 64 250 tbd call ti call ti ads62p45irgcr preview qfn rgc 64 2500 tbd call ti call ti ads62p45irgct preview qfn rgc 64 250 tbd call ti call ti (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 22-jan-2008 addendum-page 1
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of ti information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. information of third parties may be subject to additional restrictions. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. ti products are not authorized for use in safety-critical applications (such as life support) where a failure of the ti product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of ti products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by ti. further, buyers must fully indemnify ti and its representatives against any damages arising out of the use of ti products in such safety-critical applications. ti products are neither designed nor intended for use in military/aerospace applications or environments unless the ti products are specifically designated by ti as military-grade or "enhanced plastic." only products designated by ti as military-grade meet military specifications. buyers acknowledge and agree that any such use of ti products which ti has not designated as military-grade is solely at the buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. ti products are neither designed nor intended for use in automotive applications or environments unless the specific ti products are designated by ti as compliant with iso/ts 16949 requirements. buyers acknowledge and agree that, if they use any non-designated products in automotive applications, ti will not be responsible for any failure to meet such requirements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband clocks and timers www.ti.com/clocks digital control www.ti.com/digitalcontrol interface interface.ti.com medical www.ti.com/medical logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security rfid www.ti-rfid.com telephony www.ti.com/telephony rf/if and zigbee? solutions www.ti.com/lprf video & imaging www.ti.com/video wireless www.ti.com/wireless mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright 2008, texas instruments incorporated
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